Anheier, Walter
Lade...
Preferred name
Anheier, Walter
Official Name
Anheier, Walter
Alternative Name
Anheier, W.
Walter Anheier
GND
6 Ergebnisse
Einstellungen
Gerade angezeigt 1 - 6 von 6
- Some of the metrics are blocked by yourconsent settings
Item-typ:Veröffentlichung, Test produktionsbedingter Laufzeitfehler in hochintegrierten, digitalen Schaltungen(2003-12-17); ; ; The increasing clock frequencies have led to new fault effects of production defects. These so called "delay faults" have to be adressed by todays production test. The research work which was supported by Philips Semiconductors, Hamburg, provides an introduction into the problems of delay fault testing in a production environment. A test pattern generator for path delay faults has been developed. Furthermore, different classes of test quality have been defined. The investigations focus on the properties of this classes of test quality. At the end of the thesis, the next fault effects, so called signal integrity faults, are introduced which will occur as the operating clocks continue to increase. Based on their relationship with delay faults it is discussed how a test pattern generator for such faults could be constructed.Dissertation289 103 - Some of the metrics are blocked by yourconsent settings
Item-typ:Veröffentlichung, Improving Security for Elliptic Curve Implementations on Smart Cards: A Random Number Generator Test Unit(2006-07-24); ; ; We present a new random number gernator test unit for smart cards that has the same test quality (for the error types studied) as a test unit following the FIPS 140-2 standard, but with lower hardware characteristics and requires a short sample sequence.Dissertation210 108 - Some of the metrics are blocked by yourconsent settings
Item-typ:Veröffentlichung, Reduction of Crosstalk Pessimism with Consideration of Logic and Timing Correlations(2009-06-24); ; ; Accurate estimation of crosstalk has become a key issue in Static Timing Analysis of modern deep-submicron (DSM) digital circuits. The inherent logic and timing properties of the circuit are often neglected in the crosstalk estimation process resulting in an overly pessimistic analysis. False Noise Analysis aims at estimating the worst realizable crosstalk that is logically and temporally valid. Although the false noise problem has been widely studied, due to its NP-hard nature, it still lacks a very efficient solution. In this thesis, this problem of false noise is studied in detail and three novel techniques which improve the speed and accuracy of this process are proposed. The contributions of this thesis can be classified into two sections - speed improvement techniques and conservative analysis techniques.Speed improvement techniques: The novel speed improvement techniques called Simple Aggressor Ordering (SAO) and Adaptive Bounding (AB) exploit problem specific knowledge to prune a large portion of the infeasible search space of the underlying branch and bound algorithm. The beneficence of these methods lies in the fact that they simultaneously improve the speed, solvability and accuracy (stemming from the ability to solve all the cases, which are otherwise infeasible).Conservative analysis techniques: One of the drawbacks of the state-of-the-art techniques to solve the false noise problem is that they are either non-conservative or inefficient. This issue is addressed by the novel Timing Arc Based Logic Analysis (TABLA) technique that uses dedicated solvers to solve the temporal and logical problems. TABLA uses timing arcs as basic elements to perform an efficienttemporal logic analysis employing the min-max timing model using dedicated solvers for logic and timing. The proposed techniques have been implemented and tested in an industrial environment on several industrial and benchmark circuits, and results are provided.Dissertation299 197 - Some of the metrics are blocked by yourconsent settings
Item-typ:Veröffentlichung, Modelling and Test Generation for Crosstalk Faults in DSM Chips(2016-02-19); ; ; In the era of deep submicron technology (DSM), many System-on-Chip (SoC) applications require the components to be operating at high clock speeds. With the shrinking feature size and ever increasing clock frequencies, the DSM technology has led to a well-known problem of Signal Integrity (SI) more especially in the connecting layout design. The increasing aspect ratios of metal wires and also the ratio of coupling capacitance over substrate capacitance result in electrical coupling of interconnects which leads to crosstalk problems. In this thesis, first the work carried out to model the crosstalk behaviour between aggressor and victim by considering the distributed RLGC parameters of interconnect and the coupling capacitance and mutual conductance between the two nets is presented. The proposed model also considers the RC linear models of the CMOS drivers and receivers. The behaviour of crosstalk in case of under etching problem has been studied and modelled by distributing and approximating the defect behaviour throughout the nets. Next, the proposed model has also been extended to model the behaviour of crosstalk in case of one victim is influenced by several aggressors by considering all aggressors have similar effect (worst-case) on victim. In all the above cases simulation experiments were also carried out and compared with well-known circuit simulation tool PSPICE. It has been proved that the generated crosstalk model is faster and the results generated are within 10% of error margin compared to latter simulation tool. Because of the accuracy and speed of the proposed model, the model is very useful for both SoC designers and test engineers to analyse the crosstalk behaviour. Each manufactured device needs to be tested thoroughly to ensure the functionality before its delivery. The test pattern generation for crosstalk faults is also necessary to test the corresponding crosstalk faults. In this thesis, the well-known PODEM algorithm for stuck-at faults is extended to generate the test patterns for crosstalk faults between single aggressor and single victim. To apply modified PODEM for crosstalk faults, the transition behaviour has been divided into two logic parts as before transition and after transition. After finding individually required test patterns for before transition and after transition, the generated logic vectors are appended to create transition test patterns for crosstalk faults. The developed algorithm is also applied for a few ISCAS 85 benchmark circuits and the fault coverage is found excellent in most circuits. With the incorporation of proposed algorithm into the ATPG tools, the efficiency of testing will be improved by generating the test patterns for crosstalk faults besides for the conventional stuck-at faults. In generating test patterns for crosstalk faults on single victim due to multiple aggressors, the modified PODEM algorithm is found to be more time consuming. The search capability of Genetic Algorithms in finding the required combination of several input factors for any optimized problem fascinated to apply GA for generating test patterns as generating the test pattern is also similar to finding the required vector out of several input transitions. Initially the GA is applied for generating test patterns for stuck-at faults and compared the results with PODEM algorithm. As the fault coverage is almost similar to the deterministic algorithm PODEM, the GA developed for stuck-at faults is extended to find test patterns for crosstalk faults between single aggressor and single victim. The elitist GA is also applied for a few ISCAS 85 benchmark circuits. Later the algorithm is extended to generate test patterns for worst-case crosstalk faults. It has been proved that elitist GA developed in this thesis is also very useful in generating test patterns for crosstalk faults especially for multiple aggressor and single victim crosstalk faults.Dissertation368 171 - Some of the metrics are blocked by yourconsent settings
Item-typ:Veröffentlichung, Entwicklung, Untersuchung und Vergleich von Selbsttestverfahren für integrierte Sensoren in der Betriebsphase(2003-07-07); ; ; Today and more and more in the near future, analogue circuits will place great importance on integration. Technological progresses in the field of microelectronic systems make it possible to integrate both sensors and actuators directly into the circuitry production process. The development of suitable self test methods becomes necessary, if the sensor will act in security relevant or life preserving systems. In the case of an incorrect measurement, an unwanted or uncontrolled system reaction could arise. This reaction can be suppressed, if the system is monitored during the operation phase. The function control should be done during the whole operation time. The aim of this dissertation and the previous works were to improve known methods and to develop new solutions; that can provide a statement to the function of the system during the operation phase. This dissertation contains the following topics: It presents which kind of defects that occurs to an erroneous system function of the considered system. To simulate this kind of defects some error modeling concepts was developed, of which some are presented. A summary about analogue and digital test methods and how they can complement each other is given. It is described how a temperature measurement system could be tested and demonstrates new test methods and solutions developed for sensor systems which are not available for direct stimulation. One test method use the limited dynamic of system itself to make a time based correlation between following measurement values. The result of this correlation can be used as test criteria. Another new test method uses properties of a researched amplifier circuit structure to make a test during the operation phase. Furthermore it is described if and how an observation of the supply current is an adequate test criterion. Therefore a new current sensor was developed, which allows a temperature independent measurement.Dissertation450 180 - Some of the metrics are blocked by yourconsent settings
Item-typ:Veröffentlichung, Automatisierter Systementwurf in der digitalen Signalverarbeitung auf der Basis von Schaltungsstrukturen der Restklassenarithmetik(2004-01-07); ; ; Residue number arithmetic is characterized by a non-weighted number system, where long integer numbers are split into several smaller numbers with restricted numerical range. This allows the computation of long words by several smaller words, which use almost identical circuits in a parallel structure. However, the non-weighted number representation complicates sign detection, the comparison of numbers and the division operation.In this work, circuits are presented to realize sign detection, a comparison of numbers and a division with fixed values. Furthermore, circuits implementing FFT, error correction and number system conversion are shown.The concepts are based on parametrical circuit elements for residue number systems like ABIP, HYBIP and IPSP. The complexity of these three elements is analyzed for a word length in the range of 2 to 7.To carry out an automated system implementation based on circuit structures of residue number arithmetic, a synthesis tool is created. This hardware compiler can be used through a command line or a graphical user interface. The hardware compiler makes complex circuit structures available in parametrical form. Using parameterized modules for the circuit description allows for designs to be easily reused, which allows for more complex circuits. The hardware compiler can simulate and create a VHDL netlist of a circuit. In this manner a link to other synthesis tools is available.Dissertation320 308