Adiabatic Charging in SAR ADCs

Abstract

Successive Approximation Register (SAR) is an established and well-rounded (Analog-to-Digital Converter) ADC architecture allowing for medium resolution and medium conversion speed while being energy efficient and relatively small in area. Switched-capacitor (Digital-to-Analog Converter) DAC being an essential component of the SAR architecture in certain design configurations might contribute significantly to the overall ADC power consumption. Adiabatic capacitor charging is a method that allows for increasing the charging efficiency using linear voltage or constant current to charge a capacitor. A variation of this approach uses a series of small voltage steps instead of a voltage ramp, which is particularly suitable for switched-capacitor circuits as it does not require analog circuitry such as a voltage ramp generator or a current source. This work investigates the stepwise capacitor charging approach applied to DAC in SAR ADC in terms of the architectural modifications and their influence on the resulting efficiency improvement. The study begins with an estimation of the stepwise charging applied to a conventional DAC switching scheme. The average energy consumption is derived as a function of the number of charging steps and resolution, the results are verified in MATLAB. For the implementation of the approach, other switching schemes were considered, the selected monotonic switching scheme was then also modelled in MATLAB to evaluate the efficiency improvement depending on the number of charging steps in that case. Stepwise charging requires several intermediate voltage levels in addition to the regular reference voltage. The work includes the discussion and implementation of the onboard DC-DC converter and the MATLAB model includes its influence on energy savings, allowing for a design optimization as well as the selection of the converter’s configuration in regards to the number of charging steps, resolution, and DAC unit capacitor size. Finally, the work describes a fabricated IC with two proof-of-concept ADC prototypes featuring 4-step charging applied to a 10-bit monotonic SAR ADC. The circuits differ in terms of the DAC capacitance and conversion speed. The first prototype has a sampling rate of 165 kS/s and achieves SNDR of 57.63 dB. The second prototype has a sampling rate of 1 MS/s and achieves SNDR of 56.52 dB. The architecture is designed with separated circuits for the SAR register and adiabatic charging control logic in order to better differentiate the control logic penalty related to stepwise charging. To further identify the power savings in both prototypes, the 1-step versions of each prototype with adiabatic circuitry removed from the layout are simulated in CAD and compared to the 4-step counterparts. The evaluation of the first prototype shows a 26% reduction of the DAC power consumption including all the extra circuitry, whereas the second prototype establishes the limitation of the approach where the energy savings were overpowered by the control logic penalty and DC-DC converter switching losses. The work discusses this limitation in detail describing the applicability area of adiabatic charging. The proposed method allows the inclusion of these types of losses to optimize the configuration and estimate the benefits of the adiabatic switching in each case.