Specification analysis for system-level power-aware ASIC design

Abstract

The field of Electronic Design Automation (EDA) is a growing field whose growth is fueled, among many factors, by the ever increasing number of Application Specific Integrated Circuits (ASIC) that are required by digital systems. Amidst the current explosion in the design and production of Internet of Things (IoT) (typically battery powered devices), the need for power-aware design has reached critical importance. The need for a holistic view (power-aware) of the implications and challenges brought forth by the need to curb and properly manage power consumption power has revealed a need for the EDA field to explore system-level top-down based methodologies. As a response to the needs, this document presents two frameworks based on specification analysis at the system-level in order to address the holistic view of power-aware design. One of the frameworks focuses on system-level specifications written in natural language (ie. English), whereas the other focuses on system-level specifications written in a technical language (ie. SystemC). The frameworks are shown to be able to analyze these types of system-level specifications so as to aid designers in power-aware ASIC design. These frameworks encapsulate the contributions of this thesis, which are defined by the proper devising of analytical rules to parse the system-level specification so as to extract the basic underlying Power Management Strategy (PMS) laid out of by the specification under analysis. Use cases show the effectiveness of the frameworks in aiding designers targetting typical ASIC elements such as a bus, a port processor, encoders and a processor centric programmable System-on-Chip (SoC), all of them typical components of IoT devices. The document ends with a conclusion summarizing the work and pointing to possible future extensions to the frameworks and general research lines that are possibles avenues for developments in the field of specification analysis for power-aware system-level ASIC design.