Physical Modelling of Advanced SiGeTransistors
|Other Titles:||Physikalische Modellierung von fortschrittlichen SiGe-Transistoren||Authors:||Vytla, Rajeev Krishna||Supervisor:||Dieter, Silber||1. Expert:||Dieter, Silber||2. Expert:||Martin, Schneider||Abstract:||
Many demanding high speed applications like optical communication operating at 40-100 Gb/s and 77 GHz automotive radar require transistors with a cutoff frequency fT of 200 GHz or above. Additionally, these applications also need transistors with high breakdown voltages, which are used e.g. for ESD protection and driver stages. Furthermore, 77 GHz automotive radar applications require varactors with sufficiently high tuning range to be integrated on the same chip. Such an integration of high voltage transistors and varactors with high tuning range into high frequency SiGe bipolar technologies is challenging due to the requirement of a shallow collector for the high speed transistor. In this work, a novel concept with two epitaxial layers is proposed for the simultaneous integration of high speed transistors, high voltage transistors, and varactors with high tuning range on the same chip. Using this concept, high speed transistors with 209 GHz cut-off frequency have been combined with high voltage transistors providing an emitter-collector breakdown voltage of 5 V. Additionally, the same concept allowed the development and optimization of a varactor for a voltage controlled oscillator (VCO)with high tuning range of 13 GHz and sufficiently low phase noise suitable for 77 GHz automotive radar applications. Process and device simulations leading to the optimum device combination, and design considerations related to the process flow, are presented. This work also describes extensive investigations of the emitter, collector, and base for improving the speed of future high speed transistors. As a part of emitter optimization, it has been found that by using a relatively simple un-doped silicon cap instead of the conventional p-doped silicon cap the cutoff frequency fT increases by 15 GHz (10%). This is verified by simulation and experiment. Using the double epi concept, the collector thickness of the high speed transistor can be reduced independent from the requirements of the high voltage transistor. A detailed simulation study concerning the collector thickness and doping for achieving high speed is presented as a part of collector optimization. Investigations show that by using a thin collector of 40 nm and a high collector doping of 1.5 angstroem 10^18 cm-3 in the standard high speed transistor an improvement in cutoff frequency of 45 GHz can be achieved. As a result of base optimization, it has been found that the combination of lateral emitter scaling down to 80 nm, a thin emitter-base spacer of 30 nm, high doping of 2 angstroem 10^20 cm-3 in the extrinsic base link region, and extending the base contact towards the emitter increases the maximum oscillation frequency fmax of the high speed transistor up to 700 GHz, which means a doubling of the present performance.
|Keywords:||SiGe HBT, Double epi, High voltage npn,BVCE0, High speed npn, Varactor.||Issue Date:||13-Oct-2009||URN:||urn:nbn:de:gbv:46-diss000117734||Institution:||Universität Bremen||Faculty:||FB1 Physik/Elektrotechnik|
|Appears in Collections:||Dissertationen|
checked on Sep 19, 2020
checked on Sep 19, 2020
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