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  4. HDL-based Synthesis of Reversible Circuits : A Scalable Design Approach
 
Zitierlink URN
https://nbn-resolving.de/urn:nbn:de:gbv:46-00106518-15

HDL-based Synthesis of Reversible Circuits : A Scalable Design Approach

Veröffentlichungsdatum
2018-04-23
Autoren
Al-Wardi, Zaid Saleem  
Betreuer
Drechsler, Rolf  
Gutachter
Wille, Robert  
Zusammenfassung
Reversible computing is a promising research field due to its applications in several emerging technologies. Accordingly, several approaches for the design of reversible circuits have been introduced. Hardware Description Languages approach scales better than other methodologies, however, its main drawback is substantial amounts of additional circuit lines. This dissertation is an important step towards an elaborated scalable design flow of reversible circuits. In which, HDL-based design of reversible circuit is optimised, with line-awareness considered as the main objective. A line-aware programming style for a dedicated reversible hardware description language SyReC is proposed. Another contribution is a line-aware computation of HDL expressions. Reversible circuits' synthesis from a conventional hardware description language (VHDL) is examined. Finally, syntactical extensions to the dedicated hardware description language SyReC are suggested.
Schlagwörter
Reversible Circuits

; 

Synthesis

; 

Hardware Description Languages

; 

Scalable
Institution
Universität Bremen  
Fachbereich
Fachbereich 03: Mathematik/Informatik (FB 03)  
Dokumenttyp
Dissertation
Zweitveröffentlichung
Nein
Sprache
Englisch
Dateien
Lade...
Vorschaubild
Name

00106518-1.pdf

Size

1.97 MB

Format

Adobe PDF

Checksum

(MD5):9ec18a641eb982d0332af8ca8f9600a2

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