Parity-based Error Detection with Recomputation for Fault-tolerant Spaceborne Computing
|Other Titles:||Paritäts-basierte Fehlererkennung mit Neuverarbeitung für Fehlertolerante Datenverarbeitung im Weltraum||Authors:||Aydos, Gökçe||Supervisor:||Fey, Görschwin||1. Expert:||Fey, Görschwin||2. Expert:||Raik, Jaan||Abstract:||
In radiation environment (e.g., space, nuclear reactor), electronics can fail due to bitflips in the flipflops of integrated circuits. A common solution is to triplicate the flipflops and connect their outputs to a voter. If one of the three bits is flipped, then the voter outputs the majority value and tolerates the error. This method is called triple modular redundancya (TMR). TMR can cause about 300% area redundancy. An alternative way is error detection with on-demand recomputation, where the recomputation is done by repeating the failed processing request to the processing circuit. The computation is done in consecutive transactions, which we call transaction-based processing. We implemented and evaluated the aforementioned alternative approach using parity checking on the Microsemi ProASIC3 FPGA, which is often used in space applications. The results show that parity-based error detection with our system recovery approach can save up to 54% of the area overhead that would be caused by the TMR, and achieve in most circuits slightly better timing results than TMR on ProASIC3. This area saving can be the key for fitting the application to a space-constrained chip.
|Keywords:||error detection-based fault-tolerance, error detection, digital circuit, FPGA, fault-tolerance, dependability, safety, ProASIC3, bitflip, space, parity, dissertation, cross layer, transaction-based processing, triple modular redundancy, TMR, local triple modular redundancy, LTMR, parity-based error detection, PBED||Issue Date:||10-Aug-2017||URN:||urn:nbn:de:gbv:46-00106056-15||Institution:||Universität Bremen||Faculty:||FB3 Mathematik/Informatik|
|Appears in Collections:||Dissertationen|
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