Formal Verification throughout the Development of Robust Systems
Veröffentlichungsdatum
2016-12-21
Autoren
Betreuer
Gutachter
Zusammenfassung
As transistors are becomming smaller and smaller, they become more susceptible to transient faults due to radiation. A system can be modified to handle these faults and prevent errors that are visible from outside. We present a formal method for equivalence checking to verify that this modification does not change the nominal behavior of the system. On the other hand, we contribute an algorithm to formally verify that a circuit is robust against transient faults under all possible input assignments and variability. If equivalence or robustness cannot be shown, a counterexample is generated.
Schlagwörter
formal verification
;
equivalence checking
;
robustness checking
;
SAT
;
simulation
;
circuit
;
variability
;
ESL
;
PDR
Institution
Fachbereich
Dokumenttyp
Dissertation
Zweitveröffentlichung
Nein
Sprache
Englisch
Dateien![Vorschaubild]()
Lade...
Name
00105686-1.pdf
Size
1.81 MB
Format
Adobe PDF
Checksum
(MD5):e644d4793c1a0ffa7f82345474fe9fa0