From abstract systems to concrete chips: bridging gaps in abstraction techniques for design, verification and optimization with modern system-based hardware development

The increasing complexity of System-on-Chips (SoCs) requires new methods and techniques to handle the space of architectural possibilities and the need for optimization, verification, and validation. The Electronic System Level (ESL) methodology and Virtual Prototypes (VPs) have paved the way for efficient SoC development. VPs are executable specifications and prototypes of an SoC before the Hardware (HW) is developed, allowing engineers to develop Software (SW) and perform verification tasks before HW prototypes are available. However, the abstraction that enables fast simulation speeds in VPs also omits important information about the system performance or limits understanding the SoC's interaction with its environment. This has formed new gaps between the layers of abstraction that require new techniques to handle future demand in improved development techniques for SoCs. This thesis identifies such gaps and discusses emerging research questions around the methodologies and gaps between layers of abstractions. Based on a combined Register-Transfer level (RTL) and VP description, several approaches for modeling, optimization, and verification are presented. Through the presented approaches, this thesis demonstrates how the identified gaps between layers of abstraction can be bridged to reach a holistic development flow for modern SoC designs.