Low-Power Methodologies for High-Performance and Yield-Enhanced 3D Interconnects
Date Issued
2020-03-24
Author(s)
Supervisors
Referees
Abstract
A set of physically precise high-level models for the 3D-interconnect (TSV-based) power consumption and performance are presented in this thesis. Based on these models, a low-power technique is contributed, which can reduce the interconnect power consumption in modern 3D ICs by over 40 %. Despite its drastic power savings, the method results in negligible implementation costs. Additionally, optimization techniques are presented, which improve the TSV power consumption and performance simultaneously. The methods improve the performance by up to 65% while providing power savings of 17%, and this at lower costs than the best previous technique. Moreover, a low-power technique is presented, which also improves the manufacturing yield of TSVs. The method reduces the TSV-related defect rate by a factor of 17×, while additionally providing an improvement in the interconnect power consumption by over 30%.
Subjects
VLSI
;
3D Integration
;
Low-Power
;
Interconnects
;
High-Performance
;
Yield Enhancement
;
Through-Silicon Vias
Institution
Type
Dissertation
Secondary publication
No
Language
English
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Name
Thesis_Top.pdf
Size
4.63 MB
Format
Adobe PDF
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