Aging-Aware Design Methods for Reliable Analog Integrated Circuits using Operating Point-Dependent Degradation
Date Issued
2015-12-11
Author(s)
Supervisors
Referees
Abstract
The focus of this thesis is on the development and implementation of aging-aware design methods, which are suitable to satisfy current needs of analog circuit design. Based on the well known $\gm/\ID$ sizing methodology, an innovative tool-assisted aging-aware design approach is proposed, which is able to estimate shifts in circuit characteristics using mostly hand calculation schemes. The developed concept of an operating point-dependent degradation leads to the definition of an aging-aware sensitivity, which is compared to currently available degradation simulation flows and proves to be efficient in the estimation of circuit degradation. Using the aging-aware sensitivity, several analog circuits are investigated and optimized towards higher reliability. Finally, results are presented for numerous target specifications.
Subjects
CMOS
;
Reliability
;
Transistor
;
Analog
;
Aging-Aware
;
Operating Point
;
Transconductance Efficiency
Institution
Type
Dissertation
Secondary publication
No
Language
English
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00104965-1.pdf
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4.89 MB
Format
Adobe PDF
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